1. Background Discussion    NOTE: Some of the references referred in this subsection, using the reference number contained in the square brackets [ ], are listed to in the next subsection.
The continued scaling of CMOS technologies has brought about increasing uncertainties in process parameters to the point for which it is difficult to create reliable, robust design over all process variations. As integrated circuits continue to aggressively scale to smaller feature size (e.g., 65 nm, 45 nm, etc.), it is extremely difficult, if not impossible, to reliably manufacture circuits while achieving high product yield (or equivalently, low manufacturing cost). Traditional robust IC design methodologies (e.g., corner-based design and statistical design) attempt to leave sufficient performance margins to accommodate all process variations using a fixed circuit (i.e., fixed circuit topology and device size). As performance margins are increased, however, achieving high-performance IC design quickly becomes infeasible.
The expectation is that this problem will only worsen for post-CMOS technologies. Therefore, a point has been reached for which a paradigm shift is required to move today's deterministic design to more tunable design based on stochastic technique in order to facilitate high yield and high performance electronic products that are based on less reliable nano-scale devices.
Since manufacturing conditions are unknown during the design phase, they must be statistically modeled as random variables. Most existing robust design approaches attempt to statistically predict the random performance distributions and then add additional performance margins to accommodate the uncertainties.
With the increasingly large magnitude of the process fluctuations, existing robust design strategies attempt to reserve larger performance margins than ever before. As previously stated, such schemes ultimately reach a point for which achieving high-performance design becomes infeasible. For this reason, a new model for the IC design process is required to simultaneously improve circuit performance and product yield when using manufacturing processes that include significant uncertainty.
As integrated circuit (IC) technologies scale to 65 nm and beyond, process variations become increasingly critical and make it continually more challenging to create a reliable, robust design with high yield (see Background reference [1]). Process variations can be classified into two broad categories: inter-die variations and intra-die variations. Inter-die variations model the common/average variations across the die, while intra-die variations model the individual, but spatially correlated, local variations (e.g., random device mismatches) within the same die. Among all sources of variations, the random mismatches due to doping fluctuations are expected to become dominant within the next few technology generations (see Background reference [2]), as shown in FIG. 1. This is easy to anticipate because in today's technology a gate channel may contain only approximately 100 dopant atoms. Such large-scale variations must be carefully considered within today's IC design flow.
During the past two decades, various statistical design methodologies have been proposed for analog circuits (see Background references [3]-[7]). The key idea of these methods is to accurately predict random performance distributions and then leave sufficient performance margins to accommodate large-scale process variations. With scaling of CMOS below 90 nm, the traditional statistical design methodologies attempt to reserve larger performance margins than ever before, thereby making it extremely difficult (or even infeasible) to achieve a high-performance circuit design. For this reason, the idea of post-silicon tuning has been proposed and successfully applied to various applications. For example, adaptive supply voltage and adaptive body bias are two widely-used techniques to reduce delay and leakage variations for digital circuits (see Background references [8]-[10]).
Analog circuits, however, are substantially different in nature. Most analog circuit designs (e.g., differential pair, switched-capacitor amplifier, etc.) are ratio-based (see Background reference [23]); namely, their behaviors depend on the ratio between two analog devices. These analog circuits are designed to be robust to inter-die variations, but they are extremely sensitive to device mismatches. Moreover, analog layouts are based on regular structures, such as concentric layout (see Background reference [23]), which control systematic variations and make random fluctuations the dominant source of mismatch. Therefore, reducing random mismatches for analog devices (not only for transistors but also for resistors, capacitors, etc.) is a top priority for today's analog IC designs (see Background reference [11]).
The traditional approach for reducing random mismatches is to utilize large devices; that is, a larger gate channel contains more dopant atoms, thereby averaging-out random fluctuations. According to the well-known Pelgrom model (see Background references [12]-[13]), the standard deviation of random mismatch is inversely proportional to the square root of the device area: σMISMATCH˜1/sqrt(Area). Namely, if device area is increased by 100×, mismatch is only reduced by 10×. This fundamental limitation prevents analog and RF circuits from further CMOS scaling to achieve smaller area, faster speed and lower power. The challenging problem is how to more effectively reduce random mismatches such that smaller devices can be used to achieve better performance.
2. List of Related Art
The following is a listed of related art that is referred to in and/or forms some of the basis of other sections of this specification. All of these listed references are therefore incorporated by reference in their entirety for all purposes.    [1] S. Nassif, “Modeling and analysis of manufacturing variations,” IEEE CICC, pp. 223-228, 2001.    [2] Semiconductor Industry Associate, International Technology Roadmap for Semiconductors, 2005.    [3] G. Gielen and R. Rutenbar, “Computer-aided design of analog and mixedsignal integrated circuits,” Proceedings of the IEEE, vol. 88, no. 12, pp. 1825-1852, December 2000.    [4] G. Debyser and G. Gielen, “Efficient analog circuit synthesis with simultaneous yield and robustness optimization,” IEEE ICCAD, pp. 308-311, 1998.    [5] A. Seifi, K. Ponnambalam and J. Vlach, “A unified approach to statistical design centering of integrated circuits with correlated parameters,” IEEE Trans. CAS-I, vol. 46, no. 1, pp. 190-196, January 1999.    [6] F. Schenkel, M. Pronath, S. Zizala, R. Schwencker, H. Graeb and K. Antreich, “Mismatch analysis and direct yield optimization by spec-wise linearization and feasibility-guided search,” IEEE DAC, pp. 858-863, 2001.    [7] X. Li, P. Gopalakrishnan, Y. Xu and L. Pileggi, “Robust analog/RF circuit design with projection-based performance modeling,” IEEE Trans. CAD, vol. 26, no. 1, pp. 2-15, January 2007.    [8] J. Tschanz, J. Kao, S. Narendra, R. Nair, D. Antoniadis, A. Chandrakasan and V. De, “Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage,” IEEE JSSC, vol. 27, no. 11, pp. 1396-1402, November 2002.    [9] T. Chen and S. Naffziger, “Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation,” IEEE Trans. VLSI, vol. 11, no. 5, pp. 888-899, 2003.    [10] M. Mani, A. Singh and M. Orshansky, “Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization,” IEEE ICCAD, pp. 19-26, 2006.    [11] P. Kinget, “Device mismatch and tradeoffs in the design of analog circuits,” IEEE JSSC, vol. 40, no. 6, pp. 1212-1224, June 2005.    [12] M. Pelgrom, A. Duinmaijer and A. Welbers, “Matching properties of MOS transistors,” IEEE JSSC, vol. 24, no. 5, pp. 1433-1440, October 1989.    [13] P. Drennan and C. McAndrew, “Understanding MOSFET mismatch for analog design,” IEEE JSSC, vol. 38, no. 3, pp. 450-456, March 2003.    [14] S. Ray and B. Song, “A 13b linear 40 MS/s pipelined ADC with self-configured capacitor matching,” IEEE ISSCC, pp. 852-861, 2006.    [15] K. Chan and I. Galton, “A 14b 100 MS/s DAC with fully segmented dynamic element matching,” IEEE ISSCC, pp. 2390-2399, 2006.    [16] A. Dharchoudhury and S. Kang, “Worse-case analysis and optimization of VLSI circuit performance,” IEEE Trans. CAD, vol. 14, no. 4, pp. 481-492, April 1995.    [17] E. Felt, S. Zanella, C. Guardiani and A. Sangiovanni-Vincentelli, “Hierarchical statistical characterization of mixed-signal circuits using behavioral modeling,” IEEE ICCAD, pp. 374-380, 1996.    [18] M. Sengupta, S. Saxena, L. Daldoss, G. Kramer, S. Minehane and J. Chen, “Application-specific worst case corners using response surfaces and statistical models,” IEEE Trans. CAD, vol. 24, no. 9, pp. 1372-1380, September 2005.    [19] X. Li, J. Le, P. Gopalakrishnan and L. Pileggi, “Asymptotic probability extraction for nonnormal performance distributions,” IEEE Trans. CAD, vol. 26, no. 1, pp. 16-37, January 2007.    [20] M. Mckay, R. Beckman and W. Conover, “A comparison of three methods for selecting values of input variables in the analysis of output from a computer code,” Technometrics, vol. 21, no. 2, pp. 239-245, May 1979.    [21] E. Pebesma and G. Heuvelink, “Latin hypercube sampling of Gaussian random fields,” Technometrics, vol. 41, no. 4, pp. 303-312, November 1999.    [22] A. Papoulis and S. Pillai, Probability, Random Variables and Stochastic Processes, McGraw-Hill, 2001.    [23] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw, 2001.    [24] D. Bertsekas, Dynamic Programming and Optimal Control, Athena Scientific, 2005.